MoSys' 1T-SRAM(R) Embedded Memory Technology Enables Nintendo's Next Leap in Video Games; High Performance, High Density 1T-SRAM Powers Upcoming Wii Home Game Console

SUNNYVALE, Calif.--(BUSINESS WIRE)--June 19, 2006--MoSys, Inc. (Nasdaq:MOSY), the industry's leading provider of high-density system-on-chip (SoC) embedded memory solutions, today announced that Nintendo's upcoming Wii(TM) video game console uses MoSys' patented 1T-SRAM technology to implement the very high performance memory within the Wii console's graphics system.

This is the latest result from the more than six-years-long technical collaboration between the two companies. Previous generations of MoSys' 1T-SRAM technology were incorporated in Nintendo's earlier game console, the Nintendo GameCube(TM), in 1999, and shipped in multi-million quantities. The newest 1T-SRAM implementations embedded within the Wii console are fabricated using NEC Electronics' advanced 90nm CMOS-compatible embedded DRAM process technology. These high speed and ultra low latency memories are used as the main embedded memory on the graphics chip and in an additional external memory chip.

"We are pleased that Nintendo has again chosen our 1T-SRAM to power their latest generation game console," said Chet Silvestri, chief executive officer at MoSys, Inc.

"Designing the Wii console required an incredible list of breakthroughs in technology and innovation. The performance delivered by MoSys' 1T-SRAM technology is an important element of our solution," said Genyo Takeda, Senior Managing Director, General Manager, Integrated Research & Development Division at Nintendo. "The graphic performance of Wii benefits from MoSys' ability to develop highly innovative and dependable embedded memory products."

About 1T-SRAM

Available in densities up to 600Mbits, MoSys' patented 1T-SRAM technology represents the most advanced embedded memory technology in the world. It uses a single transistor cell to achieve its exceptional density while maintaining the refresh-free interface and low latency random memory access cycle time associated with traditional six-transistor SRAM cells. Embedded 1T-SRAM allows designers to get beyond the density limits of six-transistor SRAMs; it also reduces much of the circuit complexity and extra cost associated with using embedded DRAM. 1T-SRAM memories can be fabricated in either pure logic or embedded memory processes using as little as one fifth of the area of traditional six-transistor SRAM cores. In addition to the exceptional performance and density, this technology offers dramatic power consumption savings by using only a quarter of the power of traditional SRAM memories. 1T-SRAM technology is volume production proven in across multiple silicon processing generations and supported by a wide number of pure-play wafer foundries and independent Device Manufactures (IDMs).